In general, a semiconductor integrated circuit device has a phase locked loop circuit (PLL) installed therein for the purpose of generating a processing clock of a logic circuit, or generating a transmit signal clock. The phase locked loop circuit (PLL) that is installed in the semiconductor integrated circuit device includes an analog circuit (in particular, a voltage controlled oscillator (VCO)), and a calibration technique that automatically adjusts so that the PLL satisfies a desired characteristic has been known. For example, Japanese Patent Laid-Open No. 2000-49597, Japanese Patent Laid-Open No. H06-152401, and Japanese Patent Laid-Open No. 2003-78410 disclose the calibration technique of the PLL.